? semiconductor components industries, llc, 2013 august, 2013 ? rev. 2 1 publication order number: NCP1589L/d NCP1589L low voltage synchronous buck controller with light load efficiency and transient enhancement the NCP1589L is a low cost pwm controller designed to operate from a 5 v or 12 v supply. this device is capable of producing an output voltage as low as 0.8 v and converting voltage from as low as 2.5 v. it is easy to operate and provides an optimal level of integration to reduce size and cost of the power supply. it operates in ramp pulse modulation mode for superior load step and release response. in addition to fast transient response, it also includes a 1.5 a gate driver design and light load efficiency features such as adaptive non ? overlap circuitry and diode emulation. it normally operates at a range of 200 ? 500 khz in continuous current conduction mode, which reduces with current at light load for further power saving. protection features include programmable overcurrent protection, output overvoltage and undervoltage protection and input undervoltage lockout (uvlo). features ? v cc range from 4.5 v to 13.2 v ? adjustable operating frequency ? boost pin operates to 35 v ? ramp pulse modulation control ? precision 0.8 v internal reference ? adjustable output voltage ? internal 1.5 a gate drivers ? 80% max duty cycle ? input under voltage lockout ? programmable current limit ? adaptive diode mode emulation in light load ? this is a pb ? free device applications ? graphics cards ? desktop computers ? servers / networking ? dsp & fpga power supply ? dc ? dc regulator modules dfn10 case 485c marking diagram pin connections 1589l = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free device 1 boot 10 pgood 2 lx 3 ug 4 lg 9 vorpm 8 fb 7 comp/dis (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. http://onsemi.com 5 gnd 6 v cc (note: microdot may be in either location) NCP1589Lmntwg dfn10 (pb ? free) 3000 / tape & reel 1589l alyw flag
NCP1589L http://onsemi.com 2 figure 1. typical application diagram boot ug lx vcc gnd fb vorpm lg pgood v in = 2.5 v ? 19 v v cc = 4.5 v ? 13.2 v r4 c3 r3 r1 c2 r2 c1 comp/dis rocset v bst = 4.5 v ? 15 v gnd vout r9 r10 flag figure 2. detailed block diagram por uvlo pwm out latch 7 boot ug lx lg gnd rpmset ramp fb vocp fault fault fault lx vorpm vorpm pgood monitor ov and uv pgood 0.8 v (v ref ) 0.8 v (v ref ) comp/dis + ? ? + q r s 8 9 10 + ? + ? vcc 2 v vcc 10% of v ref 25% of v ref 6 1 3 2 4 5 + ? comp vprm azcd logic lx
NCP1589L http://onsemi.com 3 pin function description pin no. symbol description 1 boot supply rail for the floating top gate driver. to form a boost circuit, use an external diode to bring the desired input voltage to this pin (cathode connected to boot pin). connect a capacitor (c boot ) between this pin and the lx pin. typical values for c boot range from 0.1 f to 1 f. ensure that c boot is placed near the ic. 2 lx switch node pin. this is the reference for the floating top gate driver. connect this pin to the source of the top mosfet. also used for low side mosfet r ds(on) current detection and diode emulation. 3 ug top gate mosfet driver pin. connect this pin to the gate of the top n ? channel mosfet. 4 lg bottom gate mosfet driver pin. connect this pin to the gate of the bottom n ? channel mosfet. also used to set the overcurrent limit. 5 gnd ic ground reference. all control circuits are referenced to this pin. connect to flag. 6 vcc supply rail for the internal circuitry. operating supply range is 4.5 v to 13.2 v. decouple with a 1 f capacitor to gnd. ensure that this decoupling capacitor is placed near the ic. also low ? side mosfet drive voltage. 7 comp/dis compensation pin. this is the output of the error amplifier (ea) and the non ? inverting input of the pwm com- parator. use this pin in conjunction with the fb pin to compensate the voltage ? control feedback loop. pull this pin low for disable. 8 fb this pin is the inverting input to the error amplifier. use this pin in conjunction with the comp pin to com- pensate the voltage ? control feedback loop. connect this pin to the output resistor divider (if used) or directly to v out . 9 vorpm output voltage information for rpm threshold 10 pgood power good output. pulled low if vfb is outside 10% of 0.8 v v ref . absolute maximum ratings pin name symbol v max v min main supply voltage input vcc 15 v ? 0.3 v bootstrap supply voltage input boot 35 v wrt/gnd 40 v < 100 ns 15 v wrt/lx ? 0.3 v ? 0.3 v ? 0.3 v switching node (bootstrap supply return) lx 35 v 40 v for < 100 ns ? 5 v ? 10 v for < 200 ns high ? side driver output (top gate) ug 30 v wrt/gnd 15 v wrt/lx 40 v for < 100 ns ? 0.3 v wrt/lx ? 5 v for < 200 ns low ? side driver output (bottom gate) lg 15 v ? 0.3 v ? 5 v for < 200 ns feedback, vorpm fb, vorpm 6.0 v ? 0.3 v comp/dis comp/dis 5.5 v ? 0.3 v pgood pgood 7 v ? 0.3 v maximum ratings rating symbol value unit thermal resistance, junction ? to ? ambient r ja 165 c/w thermal resistance, junction ? to ? case r jc 45 c/w operating junction temperature range t j 0 to 150 c operating ambient temperature range t a 0 to 95 c storage temperature range t stg ? 55 to +150 c moisture sensitivity level msl 1 ? stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
NCP1589L http://onsemi.com 4 electrical characteristics (0 c < t a < 95 c; 4.5 v < [boot ? lx] < 13.2 v, 4.5 v < boot < 30 v, 0 v < lx < 21 v, c tg = c bg = 1.0 nf, for min/max values unless otherwise noted.) characteristic conditions min typ max unit v cc input voltage range 4.5 13.2 v boot voltage range 13.2 v wrt lx 4.5 30 v dv/dt on v cc ? 10 10 v/ s vref and error amplifier reference voltage vref 0.8 v output voltage accuracy reference and error amplifier excluding external resistive divider tolerance ? 1.0 1.0 % supply current v cc quiescent supply current no switching, v cc = 13.2 v 2.5 3.8 ma boot quiescent current no switching 0.1 100 a undervoltage lockout v cc uvlo threshold v cc rising 4.4 v v cc uvlo threshold v cc falling 4.0 v v cc uvlo hysteresis v cc rising or v cc falling 400 mv switching regulator ramp slope 0.5 v/ s ramp ? amplitude voltage 1.50 v minimum duty cycle 0 % maximum duty cycle 70 83 92 % lg minimum on time 200 350 ns error amplifier open loop dc gain (note 1) 80 120 db output source current output sink current v fb < 0.8 v v fb > 0.8 v 2.0 2.0 ma unity gain bandwidth (note 1) 15 mhz disable threshold 0.7 0.8 0.9 v output source current during disable 10 40 a gate drivers upper gate source boot ? lx = 5 v 1.5 a upper gate sink boot ? lx = 5 v 1.8 lower gate source v cc = 5 v 1.5 a lower gate sink v cc = 5 v 1.2 ug falling to lg rising delay tdead1 (note 1) v cc = 12 v, ug ? lx < 1.0 v, lg > 1.0 v only valid for ccm operating mode 20 30 ns lg falling to ug rising delay tdead2 (note 1) v cc = 12 v, lg < 1.0 v, ug > 1.0 v only valid for ccm operating mode 20 30 ns ug internal resistor to lx unbiased, boot ? lx = 0 45 k lx internal resistor to gnd 45 k soft ? start soft ? start time v cc > 4.5 v, comp disable threshold 2.0 2.6 ms enable to soft ? start delay (note 1) v cc > 4.5 v, comp rises and crosses disable threshold 500 s 1. guaranteed by design but not tested in production.
NCP1589L http://onsemi.com 5 electrical characteristics (0 c < t a < 95 c; 4.5 v < [boot ? lx] < 13.2 v, 4.5 v < boot < 30 v, 0 v < lx < 21 v, c tg = c bg = 1.0 nf, for min/max values unless otherwise noted.) characteristic unit max typ min conditions power good including ovp and uvp threshold output voltage logic low, sinking 4 ma 0.4 v overvoltage until pgood goes low 880 902 mv undervoltage until pgood goes low 698 720 mv pgood high upper limit hysteresis 16 mv pgood high lower limit hysteresis 16 mv ovp threshold to part disable 950 1000 1030 mv uvp threshold to part disable 570 600 630 mv power good delay (note 1) 1.0 s zero current detection (lx pin) zero current detection blank timer after tg < 1.0 v lx > 50 mv, lg on time 200 250 350 ns capture time for lx voltage (note 1) time to capture lx voltage once lg is < 1.0 v 40 ns zero current v th adjustment detection (lx pin) negative lx detection voltage vbdls 200 300 400 mv positive lx detection voltage vbdhs 0.2 0.5 1.0 v time for v th adjustment and settling time 300 khz 3.0 3.7 s zero current detection blank timer after lg < 1.0 v (note 1) blanking time after lg is < 1.0 v 40 ns initial negative current detection threshold voltage setpoint (note 1) lx ? gnd, includes 2 mv offset range ? 5.0 ? 3.0 ? 1.0 mv v th adjustable range (note 1) ? 16 0 15 mv overcurrent protection oc current source sourced from lg pin, before ss 9.5 10 10.5 a ocp programming time v cc > 4.5 v, r oscset = 60 k 1.0 5.0 ms 1. guaranteed by design but not tested in production. figure 3. dead time definition ugate to phase phase 1 v lgate tdead1 tdead2
NCP1589L http://onsemi.com 6 applications information overcurrent protection (ocp) the NCP1589L monitors the voltage across the low side mosfet and used this information to determine if there is excessive output current. the voltage across the low side mosfet is measured from the lx pin when it is conducted, and is referenced to ground. the overcurrent measurement is timed to occur at the end of the low side mosfet conduction period. if the voltage drop across the bottom mosfet exceeds the overcurrent protection threshold, then an internal counter is triggered and incremented. if the voltage drop does not exceed the threshold for the next cycle, the internal counter will be reset. the NCP1589L will latch the over current protection fault condition after 4 consecutive cycles of overcurrent events. when the NCP1589L latches an overcurrent protection fault, both the high side and low side mosfets are turned off. to reset the overcurrent protection fault, the power to the v cc pin must be cycled. the overcurrent threshold can be set externally, by varying the r ocset resistor shunted from low side gate pin to ground. during power on reset, after the v cc and boot pins both pass the undervoltage lockout threshold, the NCP1589L will source a 10 a current from lg pin through the r ocset resistor and produce a voltage. this voltage will be sampled and locked by the device as the overcurrent protection threshold. for example, if r ocset is set to 10 k , the 10 a of current will yield a 100 mv threshold, and if the voltage across the low side mosfet exceeds 100 mv at the end of the its conduction period, an overcurrent event will be detected. the ocp threshold is only associated with power on reset, and won?t be wiped out by pulling comp pin down (disabling the part). if the r ocset resistor is not present, the overcurrent protection threshold will max out at 640 mv. the recommended range for r ocset is 5 k to 60 k which yields a threshold voltage range of 50 mv to 600 mv. internal soft ? start to prevent excess inrush current during startup, the NCP1589L uses a calibrated current source with an internal soft ? start capacitor to ramp the reference voltage from 0 v to 800 mv over a period of around 4 ms. the soft ? start ramp generator will reset if the input power supply voltages reach the undervoltage lockout threshold, or if the NCP1589L is disabled by having the comp pin pulled low. startup into a precharged load during a startup, the NCP1589L will detect the residual charge on the output capacitors. instead of fully dischar ging the capacitors, the soft ? start will begin from the precharged output voltage level. for example, if the NCP1589L is configured to provide a regulated output voltage of 2.5 v, the normal soft ? start sequence will ramp the output voltage from 0 to 2.5 v in 4.2 ms; however if the output capacitors already has 1.2 v voltage, the NCP1589L will not discharge the capacitors, instead the soft ? start sequence will begin at 1.2 v and then ramp the output up to 2.5 v. power good the pgood pin is an open drain connection, with an active high output to signal the condition of the converter. pgood is pulled low during soft ? start cycle, and if there is overvoltage or undervoltage fault. if the voltage on the fb pin is within 10% of v ref (800 mv) then the pgood pin will not be pulled low. the pgood pin does not have an internal pull-up resistor. overvoltage protection (ovp) if the voltage on the fb pin exceeds the overvoltage threshold (1000 mv, 125% of v ref ), the NCP1589L will latch an overvoltage fault. during an overvoltage fault event the ug pin will be pulled low, and the lg pin will stay high until the voltage on the fb pin goes below v ref /2 (400 mv). if the overvoltage fault condition stays, the NCP1589L will continue drive the lg pin, lg will go high if fb exceeds 1000 mv, then go low when fb is below 400 mv. the power of the NCP1589L needs to be cycled up to clear the overvoltage fault. undervoltage protection (uvp) if the voltage on the fb pin falls below the undervoltage threshold after the soft ? start cycle completes, then the NCP1589L will latch an undervoltage fault. during an undervoltage fault, both the ug and lg pins will be pulled low. toggling power or comp pin will reset the undervoltage protection unit. vorpm (rpm threshold) the NCP1589L runs in rpm mode, its switching frequency is controlled by comp ripple voltage and rpm threshold. the vorpm pin is connected to the output voltage through an external divider. this voltage value is proportional to the output voltage and sets the rpm threshold voltage internally with input voltage information obtained through the switch node. the internal rpm threshold voltage (dth) is a function of both v out and v in . dth v out r9 r10 r9 v in v ramp v offset (eq. 1) where r9/r10 (figure 1) is the input voltage divider of vorpm pin v ramp is the internal ramp amplitude, v offset is the offset voltage of the threshold. each time when comp voltage exceeds rpm threshold voltage, an internal ramp signal is started and ug is driven high. when the internal ramp intercepts with comp voltage, the ug pin is reset low. the NCP1589L system operates at pseudo-fixed frequency in continuous current
NCP1589L http://onsemi.com 7 conduction mode. the output frequency can be determined by the following equation: f sw k1 ramp_slope v out r9 r10 r9 v in v ramp v offset 1 1 k2 v out v in (eq. 2) where k1, k2 is an internal trimmed value; by default, k1 = 1, k2 = 0, ramp_slope = 0.5 v/ s, v ramp = 1.5 v, v offset = 20 mv. light load operation in continuous current conduction mode, the operating frequency of the NCP1589L is almost constant. in light load, it runs in a discontinuous current mode with a scaled-down frequency as a function of the load current. internal zero current detection threshold will change adaptively to ensure the minimum amount of diode conduction period to further reduce the converter power consumption in the light load condition. feedback voltage the NCP1589L allows the output voltage to be adjusted from 0.8 v to 5 v via an external resistor divider network (r1, r4 in figure 1). the controller will try to maintain 0.8 v at the fb pin. thus, if a resistor divider circuit was placed across the feedback pin to v out , the controller will regulate the output voltage in proportion to the resistor divider ratio in order to maintain 0.8 v at the fb pin. the relation between the resistor divider network and the output voltage is show in the following equation: r4 r1 v ref v out v ref r1 0.8 v v out 0.8 v (eq. 3) figure 4. typical startup sequence vcc comp lg ug v out fb pgood internal uvlo fault 1.3 v 0.8 v normal soft ? start time ocp programming time por 4.4 v 4.0 v
NCP1589L http://onsemi.com 8 package dimensions dfn10, 3x3, 0.5p case 485c issue c 10x seating plane l d e 0.15 c a a1 e d2 e2 b 15 10 6 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. terminal b may have mold compound material along side edge. mold flashing may not exceed 30 microns onto bottom surface of terminal b. 6. details a and b show optional views for end of terminal lead at edge of package. 7. for device opn containing w option, detail b alternate construction is not applicable. ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 reference 0.10 c 0.08 c (a3) c 10x 10x 0.10 c 0.05 c a b note 3 k 10x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 2.40 2.60 e 3.00 bsc e2 1.70 1.90 e 0.50 bsc l 0.35 0.45 l1 0.00 0.03 detail a k 0.19 typ 2x 2x l1 detail a bottom view (optional) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.1746 2.6016 1.8508 0.5000 pitch 0.5651 10x 3.3048 0.3008 10x dimensions: millimeters on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 NCP1589L/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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